![]() ![]() Enabling the mixing and matching of different FinFETs within a block could increase competitiveness of TSMC's N3. ![]() With FinFlex being supported by leading EDA programs, it should be easier for chip developers to use unique FinFET configurations to introduce unique optimizations and hit their design targets.Īdjusting transistor configurations for higher performance, lower power, and optimizing area is a feature that gate-all-around (GAA) transistors support by design. Truth to be told, old school CPU creators adjusted their designs on transistor levels to maximize their performance, but such methodology was abandoned years ago when microprocessors got extremely complex. Meanwhile, once AI-enabled EDA tools gain support for FinFlex, the latter will become even more useful. TSMC says that FinFlex is supported by its electronic design automation (EDA) partners, so taking advantage of this capability should be relatively easy. But FinFlex will be particularly useful for power, performance, and costs optimizations going forward. UOP’s C 3 Oleflex technology uses catalytic dehydrogenation to convert propane to propylene and is designed to have a lower cash cost of production and higher return on investment compared to competing dehydrogenation technologies. This will enable experienced development teams to create exclusive configurations that will offer a unique PPA balance to meet their goals.įinFlex is not a replacement for customized / optimized nodes or even specialized libraries as nodes and libraries include much more just different FinFET configurations. This is not optimal for all cases, so with N3 and FinFlex, SoC designers will be able to mix and match different kinds of FinFETs within each SoC block. For example, they can use double-gate single-fin (2-1) FinFETs to reduce die size and power consumption they can choose dual-gate dual-fin (2-2) transistors if they want to balance performance, area, and power or they can pick triple-gate dual-fin (3-2) FinFETs for maximum performance, but this will mean additional power consumption and die size. When designing a system-on-chip, nowadays developers have to pick up one library / transistor type for each block within an SoC. FinFlex should enable chip developers to balance performance, power consumption, and area with exceptional granularity. One of the things that will differentiate TSMC's N3 from other foundry nodes is the company's FinFlex technology. ![]()
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